1. Field of the Invention
Embodiments of the present invention relate to a start-up circuit for a bandgap reference voltage generating circuit that can realize a fast start-up when the bandgap reference voltage generating circuit is switched from a sleep mode to an operation mode and can maintain a stable bandgap output voltage.
2. Description of Related Art
In a semiconductor integrated circuit, in order to ensure reliability of the entire system, a stable internal reference voltage should be maintained. That is, even if an external power supply voltage or temperature, or a semiconductor integration process is changed, in order for individual devices to function properly, the reference voltage used in the integrated circuit should be stably maintained. For this purpose, reference voltage generating circuits which are designed to supply a stable and constant reference voltage are provided.
Among the reference voltage generating circuits, a bandgap reference voltage generating circuit using a bipolar transistor is widely used. In general, the bandgap reference voltage generating circuit includes a start-up circuit that stably restarts the circuit when the bandgap reference voltage generating circuit is switched from a sleep mode to an operation mode. FIG. 1 is a circuit diagram of a known bandgap reference voltage generating circuit.
As shown in FIG. 1, the known bandgap reference voltage generating circuit outputs a bandgap output voltage Vbg that is used as a reference voltage. The known bandgap reference voltage generating circuit includes a temperature compensating circuit, an operational amplifier Op-Amp, a PMOS transistor MP11 (hereinafter MP represents a PMOS transistor, and MN represents an NMOS transistor), and a start-up circuit 100. The temperature compensating circuit includes bipolar transistors Q1 and Q2, and a resistor R3. The operational amplifier Op-Amp has a first input terminal Inn to which a voltage is input from an emitter of the bipolar transistor Q1, and a second input terminal Inp to which a voltage is input from an emitter of the bipolar transistor Q2 through the resistor R3. The operational amplifier Op-Amp outputs a voltage at a constant level on the basis of the input voltages. The PMOS transistor MP11 is turned on/off according to a voltage fed back from the output of the operational amplifier Op-Amp and supplies a reference current to the bipolar transistors Q1 and Q2. When the bandgap reference voltage generating circuit is switched from the sleep mode to the operation mode, the start-up circuit 100 is designed to enable the bandgap reference voltage generating circuit to stably start up.
The temperature compensating circuit is designed such that the known bandgap reference voltage generating circuit supplies a stable voltage without being influenced by a change in temperature. In particular, the temperature compensating circuit supplies, to the operational amplifier Op-Amp, a voltage of a PTAT (proportional to absolute temperature) circuit (having the bipolar transistor Q2 and the resistor R3), which increases with an increase in temperature, that is, has a positive temperature coefficient. The temperature compensating circuit also supplies a voltage of a base-emitter junction (bipolar transistor Q1), which decreases with a decrease in temperature, that is, has a negative temperature coefficient. The operational amplifier Op-Amp adds the two voltages supplied thereto and the increase and decrease in the voltages depending on the temperature cancel each other. Therefore, a stable voltage can be supplied without being influenced by the change in temperature.
The terminals of the operational amplifier Op-Amp to which the two voltages are input, that is, the first input terminal Inp and the second input terminal Inn, include MOS transistors (hereinafter, referred to as input transistors). The input transistors are designed to have the same performance. Therefore, if the two input transistors are manufactured as designed, ideally, a stable voltage can be supplied.
However, during actual manufacturing, it may be impossible to manufacture the two input transistors to ideally have the same performance. That is, a physical difference between the portions constituting the transistors, for example, a difference in channel length or source/drain depth may occur. Such a physical difference leads to a difference in electrical performance between the two input transistors, which adversely affects the stability of the reference voltage. For example, if a DC offset (i.e., a difference in drain voltage between the input transistors) is equal to or more than 0.11% of the set reference voltage, the bandgap output voltage may merely reach approximately 33% of the normal value, causing a fatal error. FIG. 2 shows a case (200) where the DC offset of the input transistors is 0% and accordingly the bandgap output voltage becomes stable, for example, at 1.2 V, and a case (210) where the DC offset is approximately 0.11% and accordingly the bandgap output voltage is merely at approximately 0.4 V. Thus, a failure occurs in the bandgap output voltage.
In the known bandgap reference voltage generating circuit, a failure occurs in the bandgap output voltage due to a difference in performance between the input transistors because the operational amplifier Op-Amp amplifies a difference in voltage at the input terminals 1000 times or more during an open-loop operation. As a result, rapid voltage drop at the output terminal of the operational amplifier Op-Amp is impaired. This will be described below in detail with reference to FIG. 1.
During the sleep mode, if the external power supply voltage pwd, which is applied to the circuit from an external source, is at 3.3 V (that is, “High” level), a voltage pwdb output through an inverter becomes 0 V (that is, “Low” level). The voltage pwdb is applied to the gates of the transistors MP12 and MN12, and the voltage pwd is applied to the gate of the transistor MP13. A PMOS transistor is turned on when a voltage at a “Low” level is applied to the gate thereof, and an NMOS transistor is turned on when a voltage at a “High” level is applied to the gate thereof. Therefore, the transistors MP12 and MN12 are turned on and off, respectively, in the sleep mode since the voltage pwdb is applied to the gates thereof, and the transistor MP13 is turned off in the sleep mode since the voltage pwd is applied to the gate thereof.
As the transistor MP12 is turned on, the source of the transistor MP12 is at the same level as the power supply voltage of 3.3 V, which is connected to the drain of the transistor MP12. Because the transistors MP15 and MN12 are turned off the 3.3 V level is maintained. Since the 3.3 V is applied to the gate of the transistor MP11, the transistor MP11 is kept turned off. Therefore, a reference current does not flow through the transistor MP11, and the bandgap output voltage Vbg is maintained at 0 V.
On the other hand, if the voltage pwd, which is applied to the circuit from an external source, becomes 0 V, the voltage pwdb becomes 3.3 V. Accordingly, because of the same principles described above, the transistor MP12 is turned off, and the transistors MP13 and MN12 in the start-up circuit are turned on. As the transistor MP13 is turned on, a current flows through the transistor MP13. Then, each of the transistors MP14 and MN13 to MN15 functions as a resistor since its gate and drain are connected with each other. Therefore, the voltage at the drain of the transistor MN13 is set at approximately 2.4V. Since the drain of the transistor MN13 is connected to the gate of the transistor MP15, as the voltage at the drain of the transistor MN13 rises to 2.4 V, the transistor MP15 is turned on. Since the drain of the transistor MP15 is connected to the source of the transistor MP12, as the transistor MP15 is turned on, a current flows from the source of the transistor MP12, which is maintained at 3.3 V, to the ground Vss through the transistors MP15 and MN12. At this time, since the transistor MP12 is turned off, the power supply voltage Vdd of 3.3 V is not supplied through the transistor MP12 and the voltage at the source of the transistor MP12 falls from 3.3 V to below 3.3V and reaches approximately 2.1 V, and accordingly the transistor MP11 is turned on. If the transistor MP11 is turned on, the reference current flows from the drain of the transistor MP11 to the operational amplifier Op-Amp along the transistor MP11, and the bandgap output voltage Vbg rises from 0 V to 1.2 V. Thus, a stable bandgap output voltage Vbg is output because the voltage at the output terminal of the operational amplifier Op-Amp (that is, the source of the transistor MP12) rapidly and stably falls, and the voltage applied to the gate of the transistor MP11 is maintained stably to keep the transistor MP11 turned on.
In the known bandgap reference voltage generating circuit, the transistor MP15 is a PMOS transistor and has a threshold voltage Vth of approximately 0.9 V. Accordingly, in a state where 2.4 V is applied to the gate of the transistor MP15, if the voltage at the drain of the transistor MP15 falls from 3.3 V and becomes less than 3.0 V, the drain-gate voltage Vdg becomes lower than the threshold voltage Vth. Therefore, a discharge driving force applied to the transistor MP12 by the transistor MP15 is weakened, and a current flows insufficiently, causing a lower voltage drop at the source of the transistor MP12.
At this time, if the DC offset between the input transistors of the operational amplifier Op-Amp occurs, voltage drop at the source of the transistor MP12 may be further reduced. This is because the output voltage of the operational amplifier Op-Amp is connected to the source of the transistor MP12 and is further increased when, during open-loop operation, the operational amplifier Op-Amp amplifies the DC offset between the input transistors 1000 times or more. Consequently, the turned-on state of the transistor MP11, whose gate is connected to the source of the transistor MP12, may be made unstable. If the transistor MP11 is made unstable, the bandgap output voltage Vbg may become significantly lower than the normal value. FIG. 2 shows the bandgap output voltages when the DC offset is 0% (200) and when the DC offset is 0.11% (210). From this, it can be seen that, when the DC offset is 0.11%, the bandgap output voltage is abnormally at 0.4 V, which is significantly lower than the ideal level of 1.2 V, when the DC offset is 0%.
This abnormal output state of the bandgap output voltage may adversely affect driving of the semiconductor circuit, which uses the bandgap output voltage as a reference voltage, and the reliability of the semiconductor device may be deteriorated.